Fall 2009 Cray XT5 Hex-core Workshop

When: Dec. 7 – 9, 2009
Where: JICS Auditorium (ORNL)
Agenda: Download (Updated: 12/10/09)
Registration: Registration has ended for this workshop

Overview

Both the DOE-supported NCCS and and the NSF-supported NICS have upgraded their Cray XT5 systems from quad-core to six-core. These powerful supercomputer systems have features which must be well understood by developers and users to enable large applications to scale to higher number of processors and achieve sustained higher performance.

NCCS and NICS will jointly sponsor a 3 day workshop covering the important issues in obtaining increased performance. In particular the following topics with be covered:

  1. XT5 architecture
  2. AMD six-core CPU
  3. XT5 NUMA issues
  4. Programming effectively for the XT5

    5. * Using OpenMP on the multicore XT5
    * Optimizing MPI performance on the Seastar II Interconnect
    * Latest Libraries for the hex cores
    * Using the latest Craypat to identify application bottlenecks
    * Strategies for improving algorithmic scaling

This workshop will have lectures from NCCS, NICS and Cray staff as well as hands-on sessions, where the staff will be available to work on your application with you. Past workshop have been extremely successful and you are encouraged to attend to get the most out of the fastest computers in the world.

Getting to ORNL

To visit ORNL, you must provide a valid photo ID. If you are a foreign national, you much provide your passport and visa at the portal and at the ORNL Visitor Center. You will not be allowed into the lab without this identification. Please park your car in the employee/visitor parking lot across the street from the Visitor Center.

Maps & Directions

Click here for maps and driving directions to Oak Ridge National Laboratory.
Transportation must be provided by attendee.

Workshop Documents and Presentations

Day 1

Fall 2009 Cray XT5 Hex-core Workshop – Ashley Barker (NCCS)
Description of AMD 6-core CPU for Application Developers – Brain Waldecker (AMD)
Cray XT Architecture – Jeff Larkin (Cray, Inc.)
Overview of NICS XT5 6-core Systems – Daniel Lucio (NICS)
A Guide to Using NCCS Jaguar System – Don Frederick (NCCS)
Introduction to Cray Portals Communication Layer – Kittrich Sheets (Cray, Inc.)
Using CrayPAT to measure application performance – Luiz DeRose (Cray, Inc.)

Day 2

Specific Optimizations for the Cray Xt5 6-Core Systems – Jeff Larkin (Cray, Inc.)
Using Cray MPI- An Application Developer’s Perspective – Mark Fahey (NICS)
Scalable Method for Ab Initio Computation of Free Energies in Nanoscale Systems – Markus Eisenback (NCCS)
Introduction to Cray Compilers – Nathan Wichman (Cray, Inc.)
Using PGI Compilers – PGI Staff
Introduction to Lustre and NCCS Spider Parallel file systems for XT5 – David Dillow (NCCS)
Using I/O on Cray XT Systems – Lonnie Crosby (NCCS)
Using a High-Level I/O library for Improved Performance: ADIOS – Jay Lofstead (Georgia Tech)

Day 3

Introduction to OpenMP on the XT5 – Christian Halloy (NICS)
Using Debuggers on XT5: DDT – David Lecomber, David Maples (Allinea)